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| TV00570002/003CDGB TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS TENTATIVE Pseudo SRAM and NOR Flash Memory Mixed Multi-Chip Package DESCRIPTION The TV00570002/003CDGB is a mixed multi-chip package containing a 33,554,432-bit pseudo static RAM and a 134,217,728-bit Nor Flash Memory. The TV00570002/003CDGB is available in a 81-pin BGA package making it suitable for a variety of applications. MCP Features * * * Power supply voltage of 2.7 to 3.3 V Operating temperature of -30 to 85C Package P-TFBGA81-0710-0.80BZ (Weight: 0.15 g) Nor Flash Memory Features * * Organization: 8M x 16 bits Power dissipation Read operating : 55 mA maximum Address Increment Read operation: 24mA maximum Page Read operating : 5 mA maximum Program / Erase operating: 15 mA maximum Standby : 10 A maximum Access time : Random : 70 ns @CL=30pF Page : 25 ns @CL=30pF Functions Simultaneous Read/Write Page read Auto-Program , Auto Page Program Auto Block Erase , Auto Chip Erase Program Suspend / Resume Erase Suspend/Resume Data polling / Toggle bit Password block protection Block Protection/Boot Block Protection Automatic Sleep, supports for hidden ROM Area Common Flash Memory Interface (CFI) Block erase architecture 8 x 8 Kbytes / 127 x 64 Kbytes Bank architecture 16 Mbits x 8 Banks Boot block architecture TV00570002CDGB : top boot block TV00570003CDGB : bottom boot block Mode control Compatible with JEDEC standard commands Erase/Program cycles 100,000 cycles typ. Pseudo SRAM Features www..com * Power dissipation * Organization : 2M x 16 bits Operating : 40 mA maximum Standby : 150 A maximum Deep power-down standby : 5 A maximum Access time : Random / Page : 70 ns / 30 ns @CL=30pF Page read operation by 8 words Deep power-down mode : Memory cell data invalid * * * * * * * * * * 2008-05-08 1/9 TV00570002/003CDGB PIN ASSIGNMENT (TOP VIEW) 1 2 3 4 5 6 7 8 A B C D E F G H J K NC NC NC A3 A2 A1 A0 CEf CE1ps NC NC A7 A6 A5 A4 VSS OE NC LB UB NC WP/ACC NC WE NC A8 A19 A9 A10 DQ6 DQ13 DQ12 DQ5 NC NC A11 A12 A13 A14 NC DQ15 DQ7 DQ14 NC NC RESET RY/ BY f CE2ps A20 NC NC DQ4 VCCps NC NC A15 A21 A22 A16 NC VSS A18 A17 DQ1 DQ9 DQ10 DQ2 NC NC NC DQ3 VCCf DQ11 NC DQ0 DQ8 www..com L NC NC NC NC NC M PIN NAMES A0 to A22 DQ0 to DQ15 CE1ps , CE2ps CEf OE WE LB , UB WP/ACC RESET RY/ BY f VCCps VCCf VSS NC Address inputs Data inputs / outputs Chip enable inputs for Pseudo SRAM Chip enable inputs for Nor Flash Memory Output enable input Write enable input Data byte control inputs for Pseudo SRAM Write protect /program acceleration input for Nor Flash Memory Hardware reset input for Nor Flash Memory Ready/Busy output for Nor Flash Memory Power supply for Pseudo SRAM Power supply for Nor Flash Memory Ground Not connected 2008-05-08 2/9 TV00570002/003CDGB PIN NAME CONVERSION TABLE MCP Pin Location Name A1 NC A2 - A3 - A4 - A5 - A6 - A7 - A8 NC B1 NC B2 NC B3 NC B4 NC B5 NC B6 NC B7 NC B8 NC C1 NC www..com C2 A7 C3 LB C4 WP/ACC C5 WE C6 A8 C7 A11 C8 - D1 A3 D2 A6 D3 UB D4 RESET D5 CE2ps D6 A19 D7 A12 D8 A15 E1 A2 E2 A5 E3 A18 E4 RY/ BY f E5 A20 E6 A9 E7 A13 E8 A21 F1 A1 F2 A4 F3 A17 F4 NC F5 NC F6 A10 F7 A14 F8 A22 32M PSRAM - - - - - - - - - - - - - - - - - A7 LB WE 128M Nor - - - - - - - - - - - - - - - - - A7 - WP/ACC WE A8 A11 - A3 A6 UB A8 A11 - A3 A6 - RESET - CE2 A19 A12 A15 A2 A5 A18 - A20 A9 A13 - A1 A4 A17 - - A10 A14 - - A19 A12 A15 A2 A5 A18 RY/ BY A20 A9 A13 A21 A1 A4 A17 - - A10 A14 A22 MCP Pin Location Name G1 A0 G2 VSS G3 DQ1 G4 NC G5 NC G6 DQ6 G7 NC G8 A16 H1 CEf H2 OE H3 DQ9 H4 DQ3 H5 DQ4 H6 DQ13 H7 DQ15 H8 NC J1 CE1ps J2 DQ0 J3 DQ10 J4 VCCf J5 VCCps J6 DQ12 J7 DQ7 J8 VSS K1 - K2 DQ8 K3 DQ2 K4 DQ11 K5 NC K6 DQ5 K7 DQ14 K8 - L1 NC L2 NC L3 NC L4 NC L5 NC L6 NC L7 NC L8 NC M1 NC M2 - M3 - M4 - M5 - M6 - M7 - M8 NC 32M SRAM A0 GND I/O2 - - I/O7 - A16 - OE 128M Nor A0 VSS DQ1 - - DQ6 - A16 CE OE I/O10 I/O4 I/O5 I/O14 I/O16 - CE1 DQ9 DQ3 DQ4 DQ13 DQ15 - DQ0 DQ10 - DQ12 DQ7 VSS - DQ8 DQ2 DQ11 NC DQ5 DQ14 - - - - - - - - - - - - - - - - - I/O1 I/O11 - VCC VDD I/O13 I/O8 GND - I/O9 I/O3 I/O12 NC I/O6 I/O15 - - - - - - - - - - - - - - - - - 2008-05-08 3/9 TV00570002/003CDGB BLOCK DIAGRAM VCCf A0~A22 VSS A0~A22 WP/ACC RESET CEf 128 Mbits FLASH Memory RY/BYf DQ0~DQ15 VCCps A0~A20 VSS www..com WE 32 Mbits PSEUDO SRAM OE CE1ps CE2ps UB LB 2008-05-08 4/9 TV00570002/003CDGB MODE SELECTION Pseudo SRAM MODE Read(Word) Read(Lower Byte) Read(Upper Byte) Write(Word) Write(Lower Byte) Write(Upper Byte) Outputs Disabled Standby Deep Power-down Standby H H H L H X X H X X L H X L L H CE1ps CE2ps OE WE LB L L H L L H X X X UB L H L L H L X X X Add DQ0~DQ7 DOUT DOUT High-Z DIN DQ8~DQ15 DOUT High-Z DOUT DIN Invalid DIN High-Z High-Z High-Z X DIN Invalid High-Z High-Z High-Z Nor Flash Memory www..com MODE Read / Page Read Standby Output Disable Write Hardware Reset / Standby Boot Block Protect CEf OE L X H H X X WE H X H (1) RESET H H X H L X WP DQ0~DQ15 DOUT High-Z High-Z DIN High-Z X L H X L X X X X X X X L X X Notes: L = VIL; H = VIH; X = VIH or VIL Does not apply when (1) Pulse input CEf = VIL and CE1ps = VIL and CE2ps = VIH at the same time. 2008-05-08 5/9 TV00570002/003CDGB ID CODE TABLE TYPE Manufacturer Code TV00570002CDGB Device Code TV00570003CDGB Verify Block Protect Note: * = VIH or VIL , L = VIL H = VIH (1) BA: Block address (2) 0001H: Protected block , 0000H: A22~A12 * * A6 L L A1 L L A0 L H CODE (HEX) 0098H 0003H 0014H Data (2) * BA (1) L L L H H L Unprotected block ABSOLUTE MAXIMUM RATINGS SYMBOL VCC PARAMETER VCCps/VCCf Power Supply Voltage (1) RANGE -0.6~3.6 (4) UNIT V V V V C W C mA C VIN Input Voltage www..com VDQ Input/Output Voltage VACC Topr PD Tsolder IOSHORT Tstg -0.6~3.6 -0.5~VCC + 0.5 ( 3.6) (2) Maximum Input Voltage for WP/ACC Operating Temperature Power Dissipation Soldering Temperature Output Short Circuit Current Storage Temperature (3) 13.0 -30~85 0.6 260 100 -55~125 Note : (1) -1.0 V for pulse width 10 ns (2) (3) (4) Do not apply VID/VACC when the supply voltage is not within the device's recommended operating voltage range Output shorted for no more than one second. No more than one output shorted at a time The potential difference of VCCps and VCCf is less than 0.5 V RECOMMENDED DC OPERATING CONDITIONS (Ta = -30~85C) SYMBOL VCC VIH VIL VACC PARAMETER VCCps/VCCf Power Supply Voltage Input High-Level Voltage Input Low-Level Voltage High Voltage for WP/ACC MIN 2.7 (2) TYP. MAX 3.3 (2) UNIT 0.7 x VCC -0.3 (1) VCC + 0.3 0.4 12.6 V 8.5 Note : (1) -1.0 V for pulse width 10 ns (2) The potential difference of VCCps and VCCf is less than 0.5 V CAPACITANCE (Ta = 25C, f = 1 MHz) SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance CONDITION VIN = GND VOUT = GND MIN TYP. MAX 17 22 UNIT pF pF Note: These parameters are sampled periodically and are not tested for every device. 2008-05-08 6/9 TV00570002/003CDGB DC CHARACTERISTICS (Ta = -30~85C, VCCps/ VCCf = 2.7 V~3.3 V) SYMBOL IIL IOHps IOLps IOhf1 IOHf2 IOLf ILO ICCO1f ICCO2f PARAMETER Input Leakage Current Pseudo SRAM Output High Current Pseudo SRAM Output Low Current Flash Output High Current (TTL) Flash Output High Current (CMOS) Flash Output Low Current Output Leakage Current Flash Random Read Current Flash Program Current CONDITION VIN = 0 V~VCCf (VCCps) VOH = VCCps - 0.5 V VOL = 0.4 V VOH = 2.4 V VOH = VCCf x 0.85 VOH = VCCf - 0.4 V VOL = 0.4 V VOUT = 0 V~VCCf (VCCps), OE = VIH CEf = VIL, IOUT = 0 mA, tcycle = 100ns CEf = VIL, IOUT = 0 mA CEf = VIL, IOUT = 0 mA MIN -0.5 MAX UNIT 1 1 A mA mA mA mA A 1.0 -0.4 -2.5 -100 4 mA A 55 15 15 70 70 15 5 24 40 25 150 5 10 10 2.5 mA mA mA mA mA mA mA mA mA mA A A A A www..com Erase Current ICCO3f Flash ICCO4f ICCO5f ICCO6f ICCO7f ICCO8f ICCO1ps ICCO2ps ICCSps ICCSDps ICCS1f ICCS2f VLKO (1) (2) (3) (4) Flash Read-While-Program Current Flash Read-While- Erase Current Flash Program-while- Erase-Suspend Current Flash Page Read Current Flash Address Increment Read Current(4) Pseudo SRAM Operating Current (2,3) VIN = VIH/VIL, IOUT = 0 mA, tcycle = 100 ns VIN = VIH/VIL, IOUT = 0 mA, tcycle = 100 ns VIN = VIH/VIL, IOUT = 0 mA CEf = VIL, IOUT = 0 mA , tRC = 100 ns CEf = VIL, IOUT = 0 mA tRC = 100 ns , tRPC = 25 ns CE1ps = VIL , CE2ps = VIH, IOUT = 0 mA CE1ps = VIL, CE2ps = VIH, Page add. Cycling, IOUT = 0 mA tRC = min tPC = min Pseudo SRAM Page Access Operating Current (2,3) Pseudo SRAM Standby Current (MOS) Pseudo SRAM Deep Power-down Standby Current Flash Standby Current Flash Standby Current (1) (Automatic Sleep Mode ) Low Voltage Lock-out Voltage CE1ps= VCCps - 0.2 V, CE2ps = VCCps - 0.2 V CE2ps = 0.2 V WP/ACC = VCCf CEf = RESET = VCCf or RESET = VSS VIH = VCCf or VIL = VSS V The device is going to Automatic Sleep Mode, when address remain steady during 150 ns. ICCO depends on the cycle time. ICCO depends on output loading. (ICCO1f+ ICCO7f x 7)8word Specified values are defined with the output open condition. See page P-1 to page P-6 for the specification of Pseudo Static RAM. See page F-1 to page F-47 for the specification of Nor Flash Memory. 2008-05-08 7/9 TV00570002/003CDGB PACKAGE DIMENSIONS P-TFBGA81-0710-0.80BZ Unit: mm 0.20 S B 10.00 INDEX www..com 4 0.15 0.10 S S 0.26 0.04 7.00 0.40 0.70 A 0.60 0.20 S A 0.10 S 0.08 INDEX B 0.46 0.05 S AB ABCDEFGHJ KLM 1 2 3 4 5 6 7 8 0.80 0.40 0.80 1.20 max 2008-05-08 8/9 TV00570002/003CDGB www..com RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 021023_D 070122EBA_R6 * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C * Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 060819_AF * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E 2008-05-08 9/9 TC51WHM516B w w w . D a t a S h e e t 4 U . c o m 32 Mbits PSEUDO STATIC RAM TC51WHM516B Organization : 2M x 16bits 2007-03-12 P-1/6 TC51WHM516B AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = -30C to 85C, VDD = 2.7 to 3.3 V) (See Note 1 to 7) SYMBOL tRC tACC tCO tOE tBA tCOE tOEE tBE tOD Read Cycle Time Address Access Time Chip Enable ( CE1 ) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z PARAMETER MIN 70 10 0 0 5 70 30 5 70 50 70 60 60 0 0 10 6 MAX 10000 70 70 25 25 20 20 20 10000 30 10000 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tODO Output Enable High to Output High-Z www..com tBD Data Byte Control High to Output High-Z tOH tPM tPC tAA tAOH tWC tWP tCW tBW tAW tAS tWR tCEH tWEH tODW Output Data Hold Time Page Mode Time Page Mode Cycle Time Page Mode Address Access Time Page Mode Output Data Hold Time Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Valid to End of Write Address Set-up Time Write Recovery Time Chip Enable High Pulse Width Write Enable High Pulse Width WE Low to Output High-Z WE High to Output Active Data Set-up Time Data Hold Time CE2 Set-up Time CE2 Hold Time CE2 Pulse Width CE2 Hold from CE1 CE2 Hold from Power On 20 ns ns ns ns ns s tOEW tDS tDH tCS tCH tDPD tCHC tCHP 0 30 0 0 300 10 0 30 ms ns s AC TEST CONDITIONS PARAMETER Output load Input pulse level Timing measurements Reference level tR, tF CONDITION 30 pF + 1 TTL Gate VDD - 0.2 V, 0.2 V VDD x 0.5 VDDx 0.5 5 ns 2007-03-12 P-2/6 TC51WHM516B TIMING DIAGRAMS READ CYCLE tRC Address A0 to A20 tACC tCO tOH CE1 CE2 tOE OE www..com WE Fix-H tOD tODO tBA UB , LB tBE DOUT I/O1 to I/O16 tBD VALID DATA OUT Hi-Z tOEE Hi-Z tCOE INDETERMINATE PAGE READ CYCLE (8 words access) tPM Address A0 to A2 Address A3 to A20 tRC tPC tPC tPC CE1 CE2 OE Fix-H WE UB , LB tBA tOEE DOUT I/O1 to I/O16 tBE Hi-Z tCOE tCO tACC DOUT tAA DOUT tAA DOUT DOUT Hi-Z tOE tAOH tAOH tAOH tBD tOH tOD tODO tAA * Maximum 8 words 2007-03-12 P-3/6 TC51WHM516B WRITE CYCLE 1 ( WE CONTROLLED) (See Note 8) tWC Address A0 to A20 tAS WE tAW tWP tWR tWEH tCW CE1 tWR tCH CE2 tBW www..com UB , LB tWR tODW DOUT I/O1 to I/O16 DIN I/O1 to I/O16 (See Note 10) Hi-Z tDS (See Note 9) tOEW (See Note 11) tDH (See Note 9) VALID DATA IN WRITE CYCLE 2 ( CE CONTROLLED) (See Note 8) tWC Address A0 to A20 tAS WE tAW tWP tWR tCEH tCW CE1 tWR tCH CE2 tBW UB , LB tBE DOUT I/O1 to I/O16 Hi-Z tCOE tDS DIN I/O1 to I/O16 (See Note 9) tDH tODW Hi-Z tWR VALID DATA IN 2007-03-12 P-4/6 TC51WHM516B Deep Power-down Timing CE1 tDPD CE2 tCS tCH Power-on Timing VDD VDD min CE1 tCHC CE2 www..com tCHP tCH Provisions of Address Skew Read In case, multiple invalid address cycles shorter than tRCmin sustain over 10s in a active status, as least one valid address cycle over tRCmin must be needed during 10s. over 10s CE1 WE Address tRCmin Write In case, multiple invalid address cycles shorter than tWCmin sustain over 10s in a active status, as least one valid address cycle over tWCmin with tWPmin must be needed during 10s. over 10s CE1 tWPmin WE Address tWCmin 2007-03-12 P-5/6 TC51WHM516B Notes: (1) (2) (3) (4) (5) (6) AC measurements are assumed tR, tF = 5 ns. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage reference levels. Data cannot be retained at deep power-down stand-by mode. If OE is high during the write cycle, the outputs will remain at high impedance. During the output state of I/O signals, input signals of reverse polarity must not be applied. If CE1 or LB / UB goes LOW coincident with or after WE goes LOW, the outputs will remain at high impedance. (7) If CE1 or LB / UB goes HIGH coincident with or before WE goes HIGH, the outputs will remain at high impedance. www..com 2007-03-12 P-6/6 TC58FVM7(T/B)DD 128 Mbits NOR FLASH MEMORY TC58FVM7TDD : Top Boot Block www..com TC58FVM7BDD : Bottom Boot Block Organization : 8M x 16bits 2008-07-24 F-1/47 TC58FVM7(T/B)DD TABLE OF CONTENTS 1 2 3 4 128M (8M x 16 BITS) CMOS FLASH MEMORY COMMAND SEQUENCES SIMULTANEOUS READ/WRITE OPERATION OPERATION MODES .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. .................................................. 1 3 4 5 Read Mode ID Read Standby Mode Auto-Sleep Mode Output Disable Mode Command Write Software Reset: Read/Reset Command Hardware Reset Comparison between Software Reset and www..com Hardware Reset 4.10 Auto-Program Mode 4.11 Auto-Page Program Mode 4.12 Program Suspend/Resume Mode 4.13 Auto Chip Erase Mode 4.14 Auto Block Erase/Auto Multi-Block Erase Modes 4.15 Erase Suspend/Erase Resume Modes 4.16 Block Protection 4.17 Hidden ROM Area 4.18 CFI (Common Flash memory Interface) 4.19 HARDWARE SEQUENCE FLAGS 5 DATA PROTECTION 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 5 5 5 5 6 6 6 6 7 7 7 8 8 8 9 11 12 15 17 5.1 5.2 5.3 6 7 Protection against Program/Erase Caused by Low Supply Voltage Protection against Malfunction Caused by Glitches Protection against Malfunction at Power-on 17 17 17 17 18 AC TEST CONDITIONS AC CHARACTERISTICS AND OPERATING CONDITIONS 7.1 7.2 7.3 7.4 7.5 8 9 10 Read cycle Command Write cycle Program and Erase cycle Hardware RESET Program and Erase characteristics 18 18 19 19 19 20 31 37 TIMING DIAGRAMS FLOWCHARTS BLOCK ADDRESS TABLES 10.1 10.2 11 TC58FVM7TDD (Top Boot Block) 1/5 TC58FVM7BDD (Bottom Boot Block) 1/5 TC58FVM7TDD (Top Boot Block) TC58FVM7BDD (Bottom Boot Block) 37 42 47 BLOCK SIZE TABLE 11.1 11.2 47 47 2008-07-24 F-2/47 TC58FVM7(T/B)DD 2. COMMAND SEQUENCES BUS COMMAND SEQUENCE WRITE CYCLES REQ'D Read/Reset Read/Reset ID Read Auto Program Auto Page Program Program Suspend Program Resume Auto Chip Erase 1 3 3 4 11 1 1 6 6 1 1 3 4 6 5 4 1 Addr. XXXh 555h 555h 555h 555h BK BK (3) (3) FIRST BUS WRITE CYCLE Data F0h AAh AAh AAh AAh B0h 30h AAh AAh B0h 30h AAh AAh AAh AAh AAh 98h SECOND BUS WRITE CYCLE Addr. Data THIRD BUS WRITE CYCLE Addr. Data FOURTH BUS WRITE CYCLE Addr. Data FIFTH BUS WRITE CYCLE Addr. Data SIXTH BUS WRITE CYCLE Addr. Data 2AAh 2AAh 2AAh 2AAh 55h 55h 55h 55h 555h BK (3) F0h 90h A0h E6h RA IA (1) RD ID (2) + (4) (6) (6) (5) (7) (7) 555h 555h 555h PA PD PD PA PA (6) PD (7) PA (6) PD (7) 555h 555h BK (3) (3) 2AAh 2AAh 55h 55h 555h 555h 80h 80h 555h 555h AAh AAh 2AAh 2AAh 55h 55h 555h BA (8) 10h 30h www..com Auto Block Erase Block Erase Suspend Block Erase Resume Hidden ROM Mode Entry Hidden ROM Program Hidden ROM Erase Hidden ROM Protect Hidden ROM Exit CFI BK 555h 555h 555h 555h 555h BK (3) 2AAh 2AAh 2AAh 2AAh 2AAh CA (10) 55h 55h 55h 55h 55h CD (11) 555h 555h 555h 555h 555h 88h A0h 80h 60h 90h PA (6) PD (7) 555h XX1Ah XXXh AAh 68h 00h 2AAh 55h BA (8) 30h + 55h 555h 555h 555h PPB Set ALL PPB Clear Verify Block Protect 5 5 3 AAh AAh AAh 555h 555h 555h 55h 55h 55h 555h 555h BA (5) 60h 60h 90h BA (5) + XX02h XX02h BA (5) 68h 60h PD(0) (4) + + 555h XX02h Notes: The system should generate the following address patterns: 555h or 2AAh on address pins A10~A0. DQ8~DQ15 are ignored. (1) RA: Read Address (2) RD: Read Data Output (3) BK: Bank Address = A22~A20 (4) IA: Bank Address and ID Read Address (A6,A1,A0) Bank Address = A22~A20 Manufacturer Code = (0,0,0) Device Code = (0,0,1) (5) ID: ID Code Output (6) PA: Program Address Input Input continuous 8 addresses from (A0, A1, A2) = (0, 0, 0) to (A0, A1, A2) = (1, 1, 1) in Page program. (7) PD: Program Data Input Input continuous 8 addresses from (A0, A1, A2) = (0, 0, 0) to (A0, A1, A2) = (1, 1, 1) in Page program. (8) BA: Block Address = A22~A12 (9) F0h: 00h is valid too. (10) CA: CFI Address (11) CD: CFI Data Output : Read Operations X : VIH or VIL (0h-Fh) 2008-07-24 F-3/47 TC58FVM7(T/B)DD 3. SIMULTANEOUS READ/WRITE OPERATION The TC58FVM7(T/B)DD features a Simultaneous Read/Write operation. The Simultaneous Read/Write operation enables the device to simultaneously write data to or erase data from a bank while reading data from another bank. The TC58FVM7(T/B)DD has a total of sixteen banks (16Mbits x 8 Banks). Banks can be switched by using the bank addresses (A22~A20). For a description of bank blocks and addresses, please refer to the Block Address Table and Block Size Table. The Simultaneous Read/Write operation cannot perform multiple operations within a single bank. The table below shows the operation modes in which simultaneous operation can be performed. Note that during Auto-Program execution or Auto Block Erase operation, the Simultaneous Read/Write operation cannot read data from addresses in the same bank which have not been selected for operation. Data from these addresses can be read using the Program Suspend or Erase Suspend function, however. In order to perform simultaneous operation during automatic operation execution, when changing a bank, it is necessary to set OE to VIH. SIMULTANEOUS READ/WRITE OPERATION www..com BANK ON WHICH OPERATION IS BEING STATUS OF PERFORMED Read Mode ID Read Mode (1) STATUS OF OTHER BANKS Auto-Program Mode Auto-Page Program Mode Program Suspend Mode Read Mode Auto Block Erase Mode Erase Suspend Mode Program during Erase Suspend Program Suspend during Erase Suspend CFI Mode (1) Only Command Mode is valid. 2008-07-24 F-4/47 TC58FVM7(T/B)DD 4. OPERATION MODES In addition to the Read, Write and Erase Modes, the TC58FVM7(T/B)DD features many functions including block protection and data polling. When incorporating the device into a design, please refer to the timing charts and flowcharts in combination with the descriptions below. 4.1. Read Mode To read data from the memory cell array, set the device to Read Mode. The device is automatically set to Read Mode immediately after power-on or on completion of an automatic operation. The Software Reset Command releases The ID Read Mode, releases the lock state when an automatic operation ends abnormally, and sets the device to Read Mode. Hardware Reset terminates operation of the device and resets it to Read Mode. When reading data without changing the address immediately after power-on, the host should input Hardware Reset or change CE from H to L. 4.2. ID Read Mode ID Read Mode is used to read the device manufacturer code and device code. The mode is useful in that it www..com allows EPROM programmers to identify the device type automatically. Inputting an ID Read command sets the specified bank to ID Read Mode. Banks are specified by inputting the bank address (BK) in the third Bus Write cycle of the Command cycle. To read an ID code, the bank address as well as the ID read address must be specified (with WP = VIH or VIL). The manufacturer code is output from address BK + 00; the device code is output from address BK + 01. From other banks, data is output from the memory cells. Access time in ID Read Mode is the same as that in Read Mode. However 1st access after command input need tWEHH+tACC. For a list of the codes, please refer to the ID Code Table. Inputting a Reset command releases ID Read Mode and returns the device to Read Mode. 4.3. Standby Mode TC58FVM7(T/B)DD has two ways to put the device into Standby Mode. In Standby Mode, DQ is put into the High-Impedance state. (1) Control using CE and RESET With the device in Read Mode, input VDD 0.3 V to CE and RESET . The device will enter Standby Mode and the current will be reduced to the standby current (IDDS1). However, if the device is in the process of performing simultaneous operation, the device will not enter Standby Mode but will instead cause the operating current to flow. (2) Control using RESET only With the device in Read Mode, input VSS 0.3 V to RESET . The device will enter Standby Mode and the current will be reduced to the standby current (IDDS1). Even if the device is in the process of performing simultaneous operation, this method will terminate the current operation and set the device to Standby Mode. This is a hardware reset and is described later. 4.4. Auto-Sleep Mode This function suppresses power dissipation during reading. If the address input does not change for 150 ns, the device will automatically enter Sleep Mode and the current will be reduced to the standby current (IDDS2). However, if the device is in the process of performing simultaneous operation, the device will not enter Standby Mode but will instead cause the operating current to flow. Because the output data is latched, data is output in Sleep Mode. When the address is changed, Sleep Mode is automatically released, and data from the new address is output. 4.5. Output Disable Mode Inputting VIH to OE disables output from the device and sets DQ to High-Impedance. 2008-07-24 F-5/47 TC58FVM7(T/B)DD 4.6. Command Write The TC58FVM7(T/B)DD uses the standard JEDEC control commands for a single-power supply E2PROM. A Command of Write is executed by inputting the address and data into the Command Register. The command is written by inputting a pulse to WE with CE = VIL and OE = VIH ( WE control). The command can also be written by inputting a pulse to CE with WE = VIL ( CE control). The address is latched on the falling edge of either WE or CE . The data is latched on the rising edge of either WE or CE . DQ0~DQ7 are valid for data input and DQ8~DQ15 are ignored. To abort input of the command sequence uses the Reset command. The device will reset the Command Register and enter Read Mode. If an undefined command is input, the Command Register will be reset and the device will enter Read Mode. 4.7. Software Reset: Read/Reset Command Initiate the software reset by inputting a Read/Reset command. The software reset returns the device from ID Read Mode or CFI Mode to Read Mode, releases the lock state if automatic operation has ended abnormally, and clears the Command Register. 4.8. Hardware Reset www..com A hardware reset initializes the device and sets it to Read Mode. When a pulse is input to RESET for tRP, the device abandons the operation which is in progress and enters the Read Mode after tREADY. Note that if a hardware reset is applied during data overwriting, such as a Write or Erase operation, data at the address or block being written to at the time of the reset will become undefined. After a hardware reset, the device enters Read Mode if RESET = VIH or Standby Mode if RESET = VIL. The DQ pins are High-Impedance when RESET = VIL. After the device has entered Read Mode, Read operations and input of any command are allowed. 4.9. Comparison between Software Reset and Hardware Reset ACTION Releases ID Read Mode or CFI Mode. Clears the Command Register. Releases the lock state if automatic operation has ended abnormally. Stops any automatic operation which is in progress. Stops any operation other than the above and returns the device to Read Mode. SOFTWARE RESET True True True False False HARDWARE RESET True True True True True 2008-07-24 F-6/47 TC58FVM7(T/B)DD 4.10. Auto-Program Mode The TC58FVM7(T/B)DD can be programmed in word units. Auto-Program Mode is set using the Program command. The program address and program data is latched in the fourth Bus Write cycle. Auto programming starts on the rising edge of the WE signal in the fourth Bus Write cycle. The Program and Program Verify commands are automatically executed by the chip. The device status during programming is indicated by the Hardware Sequence flag. To read the Hardware Sequence flag, specify the address to which the Write is being performed. During Auto Program execution, a command sequence for the bank on which execution is being performed cannot be accepted. To terminate execution, use a hardware reset. Note that if the Auto-Program operation is terminated in this manner, the data written so far is invalid. Any attempt to program a protected block is ignored. In this case, the device enters Read Mode 5.5 s after a latch of program data in the fourth Bus Write cycle. If an Auto-Program operation fails, the device remains in the programming state and does not automatically return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware reset is required to return the device to Read Mode after a failure. If a programming operation fails, the device should not be used. To build a more reliable system, the host processor should take measures to prevent subsequent use of failed blocks. The device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into www..com cells which contain 0s. If this is attempted, execution of Auto Program will fail. This is a user error, not a device error. A cell containing 0 must be erased in order to set it to 1. 4.11. Auto-Page Program Mode Auto-Page Program is a function which enables simultaneously Programming or 8words of data. In this mode, the Programming time for 128M bit is less than 60% compared with the Auto program mode. In word mode, input the page program command during first bus write cycle to third bus writes cycle. Input program data and address of (A0, A1, A2) = (0, 0, 0) in the forth bus write cycle. Input increment address and program data during the fifth bus write cycle to the eleventh bus write cycle. After input of the eleventh bus write cycle, page program operation starts. 4.12. Program Suspend/Resume Mode Program Suspend is used to enable Data Read by suspending the Write operation. The device accepts a Program Suspend command in Write Mode (including Write operations performed during Erase Suspend) but ignores the command in other modes. When the command is input, the address of the bank on which Write is being performed must be specified. After input of the command, the device will enter Program Suspend Read Mode after tSUSP. During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write is suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read are the same as usual. After completion of Program Suspend, input a Program Resume command to return to Write Mode. When inputting the command, specify the address of the bank on which Write is being performed. If the ID Read or CFI Data Read function is being used, abort the function before inputting the Resume command. On receiving the Resume command, the device returns to Write Mode and resumes outputting the Hardware Sequence flag for the bank to which data is being written. 2008-07-24 F-7/47 TC58FVM7(T/B)DD 4.13. Auto Chip Erase Mode The Auto Chip Erase Mode is set using the Chip Erase command. An Auto Chip Erase operation starts on the latch of the command in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the Hardware Sequence flag. Command input is ignored during an Auto Chip Erase. A hardware reset can interrupt an Auto Chip Erase operation. If an Auto Chip Erase operation is interrupted, it cannot be completed correctly. Hence, an additional Erase operation must be performed. Any attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not be executed and the device will enter Read mode 500 s after the latch of command in the sixth bus cycle. If an Auto Chip Erase operation fails, the device will remain in the erasing state and will not return to the Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware reset is required to return the device to Read Mode after a failure. In this case, it cannot be ascertained which block the failure occurred in. Either abandon use of the device altogether, or perform a Block Erase on each block, identify the failed blocks, and stop using them. To build a more reliable system, the host processor should take measures to prevent subsequent use of failed blocks. 4.14. Auto Block Erase Mode www..com The Auto Block Erase Mode is set using the Block Erase command. An Auto Block Erase operation starts on the latch of the command in the sixth bus cycle. All memory cells in the selected block are automatically preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the setting of the Hardware Sequence flag. When the Hardware Sequence flag is read, the addresses of the blocks on which the Auto Erase operation is being performed must be specified. All commands (except Erase Suspend) are ignored during an Auto Block Erase operation. Either operation can be aborted using a Hardware Reset. If an auto-erase operation is interrupted, it cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing. Any attempt to erase a protected block is ignored. If the selected block is protected, the Auto Erase operation will not be executed and the device will enter Read mode 100 s after the latch of command in the sixth bus cycle. If an Auto Block Erase operation fails, the device remains in the Erasing state and does not return to Read Mode. The device status is indicated by the Hardware Sequence flag. After a failure, either a Reset command or a Hardware Reset is required to return the device to Read Mode. If an Auto Block Erase operation fails, the device should not be used. To build a more reliable system, the host processor should take measures to prevent subsequent use of failed block. 4.15. Erase Suspend/Erase Resume Modes Erase Suspend Mode suspends Auto Block Erase and reads data from or writes data to an unselected block. The Erase Suspend command is allowed during an auto block erase operation but is ignored in all other oreration modes. When the command is input, the address of the bank on which Erase is being performed must be specified. In Erase Suspend Mode only a Read, Program or Resume command can be accepted. If an Erase Suspend command is input during an Auto Block Erase, the device will enter Erase Suspend Read Mode after tSUSE. The device status (Erase Suspend Read Mode) can be verified by checking the Hardware Sequence flag. If data is read consecutively from the block selected for Auto Block Erase, the DQ2 output will toggle and the DQ6 output will stop toggling and RY/ BY will be set to High-Impedance. Inputting a Write command during an Erase Suspend enables a Write to be performed to a block which has not been selected for the Auto Block Erase. Data is written in the usual manner. To resume the Auto Block Erase, input an Erase Resume command. On input of the command, the address of the bank on which the Write was being performed must be specified. On receiving an Erase Resume command, the device returns to the state it was in when the Erase Suspend command was input. If an Erase Suspend command is input during the Erase Hold Time, the device will return to the state it was in at the start of the Erase Hold Time. At this time more blocks can be specified for erasing. If an Erase Resume command is input during an Auto Block Erase, Erase resumes. At this time toggle output of DQ6 resumes and 0 is output on RY/ BY . 2008-07-24 F-8/47 TC58FVM7(T/B)DD 4.16. Block Protection TC58FVM7(T/B)DD has Block Protection that is a function for disabling writing and erasing specific blocks. Block Protection features several level of Block Protection. (1) Write Protect ( WP pin) [Hardware Protection] The TC58FVM7(T/B)DD has Hardware Block protection feature by WP =VIL. The TC58FVM7TDD protects BA133 and BA134 with WP =VIL. TC58FVM7BDD protects BA0 and BA1 with WP =VIL. This mode is released with WP =VIH. When the device is programming operation or erasing operation, WP pin has to fix to VIH or VIL. Block Protection 1 Persistent Protection Bit(PPB) [Software Protection] By using Persistent Protection Bit, protection can be set to each block. The PPBs retains the state across power cycle. Each PPB can be individually modifiable through the PPB Set command. All PPB can be cleared by the PPB Clear Command at a time. The Verify Block Protect command to the device can check the PPB status. The PPB set and the PPB clear are an auto operation same as the Auto Program and the Auto Chip Erase. An auto operation start from the command latch in the 4th write bus cycle of the PPB Set and the PPB clear. The status of the PPB set and the PPB clear are indicated by the below haradware sequence www..com flag. If an auto operation fails,either a Hidden ROM exit command or a Hardware Reset is required to return the device to Read Mode. The PPB set time is eqal to tPPAW (auto-page program time). The PPB clear time is equal to tPBEW (auto-block erase time). When PPB is locked by the PPB Lock Set command, PPB is disabled for PPB Set and PPB Clear Operation. The PPB Lock Verify command can check the PPB Lock status on the DQ1 (`1' is Set state and `0' is Clear state). Behaviors of PPB Lock differ between password protection mode and non-password protection mode. At the time of the finishing PPB Set, PPB Clear, PPB Lock Set and PPB Lock Verify, the hosts have to inputting the Hidden ROM Exit command. At the time of shipment, the PPBs and PPB Lock are settled to "0". (2) The Hardware Sequence Flags of the PPB Set DQ7 In Progress Set Complete Set Failed 0 1 0 DQ6 Toggle 1 Toggle DQ5 0 0 1 DQ4 0 0 0 DQ3 0 0 0 DQ2 1 1 1 DQ1 0 0 0 DQ0 0 0 0 RY/ BY 0 High-Z 0 The Hardware Sequence Flags of the PPB Clear DQ7 In Progress Clear Complete Clear Failed 0 1 0 DQ6 Toggle 1 Toggle DQ5 0 0 1 DQ4 0 0 0 DQ3 1 1 1 DQ2 DQ1 0 0 0 DQ0 0 0 0 RY/ BY Toggle 1 N/A 0 High-Z 0 2008-07-24 F-9/47 TC58FVM7(T/B)DD 4.16.1 Relationship of the Each Block Protection Block Protection 1 (PPB) Power-Up PPB Set PPB Clear Device Protect State 4.16.2. Block Protection Matrix www..com Hardware Protection Software Protection PPB Clear Set Clear Block Protect Status Two Boot Block Protected Protected Unprotected Protected Other Block Unprotected Protected Unprotected Protected WP L H Set 4.16.3. Verify Block Protect The Verify Block Protect command is used to ascertain whether a block is protected or unprotected. The Verify Block Protect command, which can be performed simultaneously with operations in another bank, is performed by setting the block address with A0 = A6 = VIL and A1 = VIH. If the block is protected, 01h is output. If the block is unprotected, 00h is output. The status depends on PPB, DPB, WP state. Inputting the verify block protect command sequence sets the specified bank to the Verify Block Protect mode. Inputting a Reset command releases this mode and returns the device to Read Mode. When verifying block protect across a bank boundary, a Reset command is needed at the time of the change of a bank. 2008-07-24 F-10/47 TC58FVM7(T/B)DD 4.17. Hidden ROM Area The TC58FVM7(T/B)DD features a 64-Kword hidden ROM area, which is separate from the memory cells. The area consists of one block. Data Read, Write and Protect can be performed on this block. Because Protect cannot be released, once the block is protected, data in the block cannot be overwritten. The hidden ROM area is located in the address space indicated in the HIDDEN ROM AREA ADDRESS TABLE. To access the Hidden ROM area, input a Hidden ROM Mode Entry command. The device now enters Hidden ROM Mode, allowing Read, Write, Erase and Block Protect to be executed. Write and Erase operations are the same as auto operations except that the device is in Hidden ROM Mode. To protect the hidden ROM area, use the Hidden ROM Protect Command. The status of Hidden ROM protect operation can be checked by hardware sequence flags. Hidden ROM protect time is eqal to tPPAW (auto-page program time). Note that in Hidden ROM Mode, simultaneous operation cannot be performed for BANK7 in top boot type and for BANK0 in bottom boot type. To exit Hidden ROM Mode, use the Hidden ROM Mode Exit command. This will return the device to Read Mode. HIDDEN ROM AREA ADDRESS TABLE TYPE www..com TC58FVM7TDD TC58FVM7BDD BOOT BLOCK ARCHITECTURE TOP BOOT BLOCK BOTTOM BOOT BLOCK ADDRESS RANGE 7F0000h~7FFFFFh 000000h~00FFFFh SIZE 64 Kwords 64 Kwords The Hardware Sequence Flags of the Hidden ROM Protect DQ7 In Progress Protect Complete Protect Failed 0 1 0 DQ6 Toggle 1 Toggle DQ5 0 0 1 DQ4 0 0 0 DQ3 0 0 0 DQ2 1 1 1 DQ1 0 0 0 DQ0 0 0 0 RY/ BY 0 High-Z 0 2008-07-24 F-11/47 TC58FVM7(T/B)DD 4.18. CFI (Common Flash memory Interface) The TC58FVM7(T/B)DD conforms to the CFI specifications. To read information from the device, input the Query command followed by the address. To exit this mode, input the Reset command. CFI CODE TABLE 1 (Continue) ADDRESS A6~A0 10h 11h 12h 13h 14h 15h 16h 17h www..com 18h 19h 1Ah DATA DQ15~DQ0 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h DESCRIPTION ASCII string "QRY" Primary OEM command set 2: AMD/FJ standard type Address for primary extended table Alternate OEM command set 0: none exists Address for alternate OEM extended table VDD (min) (Write/Erase) DQ7~DQ4: 1 V DQ3~DQ0: 100 mV VDD (max) (Write/Erase) DQ7~DQ4: 1 V DQ3~DQ0: 100 mV VPP (min) voltage VPP (max) voltage Typical time-out per single word write (2 s) Typical time-out for minimum size buffer write (2 s) Typical time-out per individual block erase (2 ms) Typical time-out for full chip erase (2 ms) Maximum time-out for word write (2 times typical) Maximum time-out for buffer write (2 times typical) Maximum time-out per individual block erase (2 times typical) Maximum time-out for full chip erase (2 times typical) Device Size (2 byte) 18h:128Mbit Flash device interface description 1: x 16 Maximum number of bytes in multi-byte write (2 ) N N N N N N N N N N 1Bh 0027h 1Ch 0033h 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 0000h 0000h 0004h 0000h 000Ah 0000h 0004h 0006h 0004h 0004h 0018h 0001h 0000h 0004h 0000h 2008-07-24 F-12/47 TC58FVM7(T/B)DD CFI CODE TABLE 2(Sequel) ADDRESS A6~A0 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 40h 41h 42h DATA DQ15~DQ0 0002h 0007h 0000h 0040h 0000h 007Eh 0000h 0000h 0002h 0050h 0052h 0049h 0031h 0031h DESCRIPTION Number of erase block regions within device Erase Block Region 1 information Bits 0~15: y = block number Bits 16~31: z = block size (z x 256 bytes) Erase Block Region 2 information ASCII string "PRI" www..com 43h 44h Major version number, ASCII Minor version number, ASCII Address-Sensitive Unlock 0: Required 1: Not required Erase Suspend 0: Not supported 1: For Read-only 2: For Read & Write Block Protect 0: Not supported X: Number of blocks per group Block Temporary Unprotect 0: Not supported 1: Supported Block Protect/Unprotect scheme Simultaneous operation 0: Not supported 1: Supported Burst Mode 0: Not supported Page Mode 0: Not supported 1: Supported VACC (min) voltage DQ7~DQ4: 1 V DQ3~DQ0: 100 mV VACC (max) voltage DQ7~DQ4: 1 V DQ3~DQ0: 100 mV Top/Bottom Boot Block Flag X = 2: Bottom Boot Block: TC58FVM7BDD X = 3: Top Boot Block: TC58FVM7TDD Program Suspend 0: Not supported 1: Supported 45h 0000h 46h 0002h 47h 0001h 48h 0000h 49h 0007h 4Ah 0001h 4Bh 0000h 4Ch 0001h 4Dh 0085h 4Eh 00C6h 4Fh 000xh 50h 0001h 2008-07-24 F-13/47 TC58FVM7(T/B)DD CFI CODE TABLE 3(Sequel) ADDRESS A6~A0 DATA DQ15~DQ0 Bank Organization 00h: Data at 4Ah is zero X: Number of Banks Bank0 Region information XX: Number of blocks Bank0 Bank1 Region information Number of blocks Bank1 Bank2 Region information Number of blocks Bank2 Bank3 Region information Number of blocks Bank3 Bank4 Region information Number of blocks Bank4 Bank5 Region information Number of blocks Bank5 Bank6 Region information Number of blocks Bank6 Bank7 Region information XX: Number of blocks Bank7 DESCRIPTION 57h 0008h 58h 00XXh TOP : 10h BOTTOM:27h 59h 0010h n=16 5Ah 0010h n=16 5Bh 0010h n=16 5Ch www..com 5Dh 0010h n=16 0010h n=16 5Eh 0010h n=16 5Fh 00XXh TOP : 27h BOTTOM:10h 2008-07-24 F-14/47 TC58FVM7(T/B)DD 4.19. HARDWARE SEQUENCE FLAGS The TC58FVM7(T/B)DD has a Hardware Sequence flag which allows the device status to be determined during an auto mode operation. The output data is read out using the same timing as that used when CE = OE = VIL in Read Mode. The RY/ BY output can be either High or Low. The device re-enters Read Mode automatically after an auto mode operation has been completed successfully. The Hardware Sequence flag is read to determine the device status and the result of the operation is verified by comparing the read-out data with the original data. STATUS Auto Programming/Auto Page Programming DQ7 DQ6 DQ5 DQ3 DQ2 RY/ BY 0 High-Z 0 0 High-Z High-Z 0 0 0 0 0 DQ7 (4) Toggle Data Toggle Toggle 1 Data Toggle Toggle Toggle Toggle Toggle 0 Data 0 0 0 Data 0 0 1 1 1 0 Data 1 1 0 Data 0 0 0 1 0 1 Data Toggle 1 Toggle Data Toggle 1 1 N/A N/A Read in Program Suspend In Auto Erase In Progress www..com (1) Data Selected (2) (3) 0 0 1 Data DQ7 DQ7 DQ7 0 DQ7 (4) Auto Erase Not-selected Selected Read In Erase Suspend Programming Not-selected Selected Not-selected Auto Programming/Auto Page Programming Time Limit Exceeded Auto Erase Programming in Erase Suspend Notes:DQ outputs cell data and RY/ BY goes High-Impedence when the operation has been completed. DQ0 and DQ1 pins are reserved for future use. 0 is output on DQ0, DQ1 and DQ4. (1) Data output from an address to which Write is being performed is undefined. (2) Output when the block address selected for Auto Block Erase is specified and data is read from there. (3) Output when a block address not selected for Auto Block Erase of same bank as selected block is specified and data is read from there. During Auto Chip Erase, all blocks are selected. (4) In case of Page program operation is program data of (A0, A1, A2) = (1, 1, 1) in eleventh bus write cycle. 4.19.1. DQ7 ( DATA polling) During an Auto-Program or auto-erase operation, the device status can be determined using the data polling function. DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto-Program operation, DQ7 outputs inverted data during the programming operation and outputs actual data after programming has finished. In an auto-erase operation, DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase operation has finished. If an Auto-Program or auto-erase operation fails, DQ7 simply outputs the data. When the operation has finished, the address latch is reset. Data polling is asynchronous with the OE signal. 4.19.2. DQ6 (Toggle bit 1) The device status can be determined by the Toggle Bit function during an Auto-Program or auto-erase operation. The Toggle bit begins toggling on the rising edge of WE in the last bus cycle. DQ6 alternately outputs a 0 or a 1 for each OE access while CE = VIL while the device is busy. When the internal operation has been completed, toggling stops and valid memory cell data can be read by subsequent reading. If the operation fails, the DQ6 output toggles. If an attempt is made to execute an Auto Program operation on a protected block, DQ6 will toggle for around 3 s. It will then stop toggling. If an attempt is made to execute an auto chip erase operation on a protected all block, DQ6 will toggle for around 300 s. It will then stop toggling. After toggling has stopped the device will return to Read Mode. If an attempt is made to execute an auto block erase operation on a protected block, DQ6 will toggle for around 3 s. It will then stop toggling. After toggling has stopped the device will return to Read Mode. 2008-07-24 F-15/47 TC58FVM7(T/B)DD 4.19.3. DQ5 (internal time-out) If an Auto-Program or auto-erase operates normally, DQ5 outputs a 0. If the internal timer times out during a Program or Erase operation, DQ5 outputs a 1. This indicates that the operation has not been completed within the allotted time. Any attempt to program a 1 into a cell containing a 0 will fail (see Auto-Program Mode). In this case, DQ5 outputs a 1. In this case, DQ5 doesn't indicate defective device but mistaken usage. After an Auto-Program or auto-erase operation ends normally, the device outputs actual cell array data. Therefor only with the data of DQ5 can't specify whether cell array data or hardware sequence flag. The hosts shuold check the state of device whether progrress or not, using DQ7, DQ6, or RY/ BY . In the case of internal time-out, either hardware reset or a software Reset command is required to return the device to Read Mode. 4.19.4. DQ3 (Block Erase) DQ3 is used to indicate whether the device is in Auto Erase Mode or Erase Suspend Mode. DQ3 outputs a 1 when the Auto Block Erase or the Auto Chip Erase operation starts. If data is read from the block selected for Auto Block Erase while the device is in Erase Suspend Mode, the DQ3 output a 0. Moreever, DQ3 outputs a 0 regardless of the block at the Erase Suspend Programming mode. DQ3 outputs a 1 if the Erase operation fails, and outputs a 0 if the Program in Erase Suspend operation fails. www..com 4.19.5. DQ2 (Toggle bit 2) DQ2 is used to indicate which blocks have been selected for Auto Block Erase or to indicate whether the device is in Erase Suspend Mode. If data is read continuously from the selected block during an Auto Block Erase, the DQ2 output will toggle. Now 1 will be output from non-selected blocks; thus, the selected block can be ascertained. If data is read continuously from the block selected for Auto Block Erase while the device is in Erase Suspend Mode, the DQ2 output will toggle. Because the DQ6 output is not toggling, it can be determined that the device is in Erase Suspend Mode. If data is read from the address to which data is being written during Erase Suspend in Programming Mode, DQ2 will output a 1. 4.19.6. RY/BY (READY/ BUSY ) The TC58FVM7(T/B)DD has a RY/ BY signal to indicate the device status to the host processor. A 0 (Busy state) indicates that an Auto-Program or auto-erase operation is in progress. A 1 (Ready state) indicates that the operation has finished and that the device can now accept a new command. RY/ BY outputs a 0 when an operation has failed. RY/ BY outputs a 0 after the rising edge of WE in the last command cycle. During an Auto Block Erase operation, commands other than Erase Suspend are ignored. RY/ BY outputs a 1 during an Erase Suspend operation. The output buffer for the RY/ BY pin is an open-drain type circuit, allowing a wired-OR connection. A pull-up resistor must be inserted between VDD and the RY/ BY pin. 2008-07-24 F-16/47 TC58FVM7(T/B)DD 5. DATA PROTECTION The TC58FVM7(T/B)DD includes a function which guards against malfunction or data corruption. 5.1. Protection against Program/Erase Caused by Low Supply Voltage To prevent malfunction at power-on or power-down, the device will not accept commands while VDD is below VLKO. In this state, command input is ignored. If VDD drops below VLKO during an Auto Operation, the device will terminate Auto-Program execution. In this case, Auto operation is not executed again when VDD returns to recommended VDD voltage. Therefore, command need to be input to execute Auto operation again. When VDD > VLKO, make up countermeasure to be input accurately command in system side please. 5.2. Protection against Malfunction Caused by Glitches To prevent malfunction write during operation caused by noise from the system, the device will not accept pulses shorter than 3 ns (Typ.) input on WE , CE or OE . However, if a glitch exceeding 3 ns (Typ.) occurs and the glitch is input to the device malfunction write may occur. The device uses standard JEDEC commands. It is conceivable that, in extreme cases, system noise may be www..com misinterpreted as part of a command sequence input and that the device will acknowledge it. Then, even if a proper command is input, the device may not operate. To avoid this possibility, clear the Command Register before command input. In an environment prone to system noise, Toshiba recommends input of a software or hardware reset before command input. 5.3. Protection against Malfunction at Power-on To prevent damage to data caused by sudden noise at power-on, when power is turned on with WE = CE =VIL the device does not latch the command on the first rising edge of WE or CE . Instead, the device automatically Resets the Command Register and enters Read Mode. 6. AC TEST CONDITIONS PARAMETER Input Pulse Level Input Pulse Rise and Fall Time (10%~90%) Timing Measurement Reference Level (input) Timing Measurement Reference Level (output) Output Load CONDITION VDD, 0.0 V 5 ns VDD/2, VDD/2 VDD/2, VDD/2 CL (30 pF) + 1 TTL Gate 2008-07-24 F-17/47 TC58FVM7(T/B)DD 7. AC CHARACTERISTICS AND OPERATING CONDITIONS 7.1. Read Cycle Symbol tRC tPRC tACC tCE tOE tPACC tOEH tCEE Read Cycle Time Page Read Cycle Time Address Access Time CE Access Time OE Access Time Page Access Time OE High-Level Hold Time (read) CE to Output Low-Z Parameter MIN 70 25 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns 70 70 25 25 0 0 0 0 0 tOEE OE to Output Low-Z www..com tOH Output Data Hold Time tAOH tDF1 tDF2 Output Data Hold Time (Page Read) CE to Output High-Z OE to Output High-Z 25 25 7.2. Command Write cycle Symbol tCMD tAS tAH tDS tDH tWELH tWEHH tCES tCEH tCELH tCEHH tWES tWEH tOES tVDS Parameter Command Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Set-up Time WE Low-Level Hold Time WE High-Level Hold Time CE Set-up Time to WE Active CE Hold Time from WE High Level CE Low-Level Hold Time CE High-Level Hold Time WE Set-up time to CE Active WE Hold Time from CE High Level OE Set-up Time VDD Set-up Time ( WE Control) ( WE Control) ( WE Control) ( WE Control) ( CE Control) ( CE Control) ( CE Control) ( CE Control) MIN 70 0 30 30 0 30 20 0 0 30 20 0 0 0 500 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns s 2008-07-24 F-18/47 TC58FVM7(T/B)DD 7.3. Program and Erase cycle Symbol tOEHP tOEHT tCEHT tAHT tAST tBUSY Program/Erase Valid to RY / BY Delay during Suspend Mode tRB tSUSP RY / BY Recovery Time Program Suspend Command to Suspend Mode Parameter OE High Level Hold Time (Polling) OE High Level Hold Time (Toggle Read) CE High Level Hold Time (Toggle Read) Address Hold Time (Toggle) Address Set-up Time (Toggle) Program/Erase Valid to RY / BY Delay MIN 10 20 20 0 0 MAX UNIT ns ns ns ns ns ns ns ns s s s s s 90 500 0 5.5 5.5 1 25 1 tSUSPA Page Program Suspend Command to Suspend Mode www..com tRESP Program Resume Command to Program Mode tSUSE tRESE Erase Suspend Command to Suspend Mode Erase Resume Command to Erase Mode 7.4. Hardware RESET Symbol tREADY tREADY tRP tRH tRPD Parameter Read Mode Recovery Time from RESET (During Auto Operation) Read Mode Recovery Time from RESET During Non Auto Operation RESET Low Level Hold Time Recovery Time from RESET RESET goes Low to Standby Mode MIN MAX 25 500 UNIT s ns ns ns s 500 50 20 7.5. Program and Erase characteristics SYMBOL tPPW tPPAW tPCEW tPBEW tEW PARAMETER Auto-Program Time (Word Mode) Auto-Page program time Auto Chip Erase Time (1) (1) MIN TYP. 12 60 162 1.2 MAX 300 2400 675 5 (2) UNIT s s s s Cycle. Auto Block Erase Time Erase/Program Cycle 10 5 (1) Auto Chip Erase Time and Auto Block Erase Time include internal pre program time. (2) Minimum interval between resume and the following suspend command is 150 s. If it's shorter than 150 s, auto block erase time is expand more than maximum(5 s). 2008-07-24 F-19/47 TC58FVM7(T/B)DD 8. TIMING DIAGRAMS VIH or VIL Data invalid Read/ID Read Operation tRC Address tACC tCE CE tOE tOEE OE tCEE tOEH tDF2 tDF1 tOH www..com WE DOUT Hi-Z Output data Valid Hi-Z Page Read Operation Address(A3-22))) tRC Address(0-2) tACC tCE CE tPRC tPRC tPRC tDF1 tOE OE tDF2 WE tOH tPACC tPACC tPACC DOUT Hi-Z DOUT DOUT DOUT DOUT DOUT Hi-Z tAOH tAOH 2008-07-24 F-20/47 TC58FVM7(T/B)DD Command Write Operation This is the timing of the Command Write Operation. The timing which is described in the following pages is essentially the same as the timing shown on this page. WE Control tCMD Address tAS Command address tAH CE tCES tCEH WE www..com tWELH tDS DIN tVDS VDD tDH tWEHH Command data CE Control tCMD Address tAS Command address tAH CE tCELH tWES WE tDS DIN tVDS VDD tDH tWEH tCEHH Command data 2008-07-24 F-21/47 TC58FVM7(T/B)DD ID Read Operation (input command sequence) Address 555h tCMD 2AAh BK + 555h BK + 00h tRC BK + 01h CE OE tOES WE DIN AAh 55h 90h Manufacturer code Device code www..com DOUT Hi-Z Read Mode (input of ID Read command sequence) ID Read Mode (Continued) Address 555h tCMD 2AAh 555h CE OE WE DIN AAh 55h F0h DOUT Hi-Z ID Read Mode (input of Reset command sequence) Read Mode BK: Bank address 2008-07-24 F-22/47 TC58FVM7(T/B)DD Read after command input (Only Hidden Rom/CFI Read) Address Last command address CE OE WE tWEHH+tACC DOUT Command data Hi-Z DOUT valid Hi-Z www..com 2008-07-24 F-23/47 TC58FVM7(T/B)DD Auto-Program Operation ( WE Control) Address 555h tCMD 2AAh 555h PA PA CE OE tOES WE tOEHP tPPW DIN AAh 55h A0h PD www..com DOUT tVDS VDD Notes: PA: Program address PD: Program data Hi-Z DQ7 DOUT Auto Chip Erase/Auto Block Erase Operation ( WE Control) Address 555h tCMD 2AAh 555h 555h 2AAh 555h/BA CE OE tOES WE DIN tVDS VDD AAh 55h 80h AAh 55h 10h/30h Notes: BA: Block Address 2008-07-24 F-24/47 TC58FVM7(T/B)DD Auto Page Program Operation ( WE Control) Address(A3-22) tCMD PA PA Address(A0-2) 555h 2AAh 555h 0h 1h 2h 3h 4h 5h 6h 7h 7h CE tOEHP www..com OE tOES tPPAW WE DIN AAh 55h E6h PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 DOUT tVDS Hi-Z DQ7 DOUT VDD Notes: PA: Program address PD: Program Data 2008-07-24 F-25/47 TC58FVM7(T/B)DD Auto-Program Operation ( CE Control) Address 555h tCMD 2AAh 555h PA PA CE tPPW OE tOES tOEHP WE DIN www..com AAh 55h A0h PD DOUT tVDS VDD Note: PA: Program address PD: Program data Hi-Z DQ7 DOUT Auto Chip Erase/Auto Block Erase Operation ( CE Control) Address 555h tCMD 2AAh 555h 555h 2AAh 555h/BA CE OE tOES WE DIN tVDS VDD AAh 55h 80h AAh 55h 10h/30h Note: BA: Block address for Auto Block Erase operation 2008-07-24 F-26/47 TC58FVM7(T/B)DD Auto Page Program Operation ( CE Control) Address(A3-22) tCMD PA PA Address(A0-2) 555h 2AAh 555h 0h 1h 2h 3h 4h 5h 6h 7h 7h CE tOEHP www..com OE tOES tPPAW WE DIN AAh 55h E6h PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 DOUT tVDS Hi-Z DQ7 DOUT VDD Notes: PA: Program address PD: Program data 2008-07-24 F-27/47 TC58FVM7(T/B)DD Program/Erase Suspend Operation Address BK RA CE OE WE tOE DIN B0h tCE www..com DOUT Hi-Z tSUSP/tSUSE DOUT Hi-Z RY / BY Program/Erase Mode RA: Read address Suspend Mode Program/Erase Resume Operation Address RA BK PA/BA CE OE tOES WE tDF1 tDF2 DIN 30h tCE DOUT DOUT Hi-Z Flag Hi-Z tOE tRESP/tRESE RY / BY Suspend Mode PA: Program address BK: Bank address BA: Block address RA: Read address Flag: Hardware Sequence flag Program/Erase Mode 2008-07-24 F-28/47 TC58FVM7(T/B)DD RY/BY during Auto Program/Erase Operation CE Command input sequence WE tBUSY During operation RY/ BY Hardware Reset Operation (At the Auto Operation) www..com WE tRB RESET tRP tREADY RY/ BY Read after RESET tRC Address tRH RESET tACC tOH DOUT Hi-Z Output data valid 2008-07-24 F-29/47 TC58FVM7(T/B)DD Hardware Sequence Flag ( DATA Polling) Address Last Command Address tCMD PA/BA CE tCE tOE OE tOEHP WE tPPW/ tPPAW/tPCEW/tPBEW DIN Last Command Data tDF1 tDF2 tACC tOH www..com DQ7 DQ7 Valid Valid DQ0~DQ6 tBUSY Invalid Valid Valid RY/BY PA: Program address BA: Block address Hardware Sequence Flag (Toggle bit) Address tAST CE tAHT tOEHT tAHT OE tOEH WE tCE tOE DIN Last Command Data DQ2/6 tBUSY RY / BY Toggle Toggle Toggl Stop* Toggle Valid *DQ2/DQ6 stops toggling when auto operation has been completed. 2008-07-24 F-30/47 TC58FVM7(T/B)DD 9. FLOWCHARTS Auto-Program Start Auto-Program Command Sequence (see below) DATA Polling or Toggle Bit Address = Address + 1 No Last Address? Yes Auto-Program Completed www..com Auto-Program Command Sequence (address/data) 555h/AAh 2AAh/55h 555h/A0h Program Address/ Program Data 2008-07-24 F-31/47 TC58FVM7(T/B)DD Auto-Page Program START Auto page program command sequence (see below ) DATA Polling or Toggle Bit Address = Address + 1 NO Last address? Yes Auto-Program Completed www..com 555h/AAh 2AAh/55h 555h/E6h Program address (A2=0,A1=0,A0=0) / Program data Program address (A2=0,A1=0,A0=1) / Program data Program address (A2=0,A1=1,A0=0) / Program data Program address (A2=0,A1=1,A0=1) / Program data Program address (A2=1,A1=0,A0=0) / Program data Program address (A2=1,A1=0,A0=1) / Program data Program address (A2=1,A1=1,A0=0) / Program data Program address (A2=1,A1=1,A0=1) / Program data 2008-07-24 F-32/47 TC58FVM7(T/B)DD Auto Erase Start Auto Erase Command Sequence (see below) DATA Polling or Toggle Bit Auto Erase Completed www..com Auto Chip Erase Command Sequence (address/data) Auto Block Erase Command Sequence (address/data) 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Block Address/30h 2008-07-24 F-33/47 TC58FVM7(T/B)DD DQ7 DATA Polling Start Read Byte (DQ0~DQ7) Addr. = VA Yes DQ7 = Data? No No DQ5 = 1? Yes Read Byte (DQ0~DQ7) Addr. = VA 1) 1) : DQ7 must be rechecked even if DQ5 = 1 because DQ7 may change at the same time as DQ5. Yes www..com DQ7 = Data? No Fail Pass DQ6 Toggle Bit Start Read Byte (DQ0~DQ7) Addr. = VA No DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Byte (DQ0~DQ7) Addr. = VA 1) 1) : DQ6 must be rechecked even if DQ5 = 1 because DQ6 may stop toggling at the same times that DQ5 changes to 1. No DQ6 = Toggle? Yes Fail Pass VA: Valid address for programming Any of the addresses within the block being erased during a Block Erase operation "Don't care" during a Chip Erase operation 2008-07-24 F-34/47 TC58FVM7(T/B)DD Hidden ROM Exit Command Input START 555h/AAh 2AAh/55h 555h/90h www..com 555h/00h FINISH 2008-07-24 F-35/47 TC58FVM7(T/B)DD PPB Set Command Sequence START 555h/AAh 2AAh/55h 555h/60h PPB Set Command Sequence 4th Bus Write Cycle (BA+02n/68h) www..com DATA Polling or Toggle Bit No DQ7 = 1? Yes HiddenROM Exit Command No DQ5 = 1? Yes HiddenROM Exit Command PPB Set Complete Device Failed PPB Clear Command Sequence START 555h/AAh 2AAh/55h 555h/60h PPB Clear Command Sequence 4th Write Cycle (xx02h/60h) DATA Polling or Toggle Bit No DQ7 = 1? Yes HiddenROM Exit Command No DQ5 = 1? Yes HiddenROM Exit Command PPB Clear Complete Device Failed 2008-07-24 F-36/47 TC58FVM7(T/B)DD 10. BLOCK ADDRESS TABLES * : VIH or VIL 10.1. TC58FVM7TDD (Top Boot Block) 1/5 BLOCK ADDRESS BANK # BLOCK # BANK ADDRESS A22 BA0 BA1 BA2 BA3 BA4 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A21 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A20 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H A19 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H A18 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H A17 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H A16 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H A15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ADDRESS RANGE A14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 000000h~00FFFFh 010000h~01FFFFh 020000h~02FFFFh 030000h~03FFFFh 040000h~04FFFFh 050000h~05FFFFh 060000h~06FFFFh 070000h~07FFFFh 080000h~08FFFFh 090000h~09FFFFh 0A0000h~0AFFFFh 0B0000h~0BFFFFh 0C0000h~0CFFFFh 0D0000h~0DFFFFh 0E0000h~0EFFFFh 0F0000h~0FFFFFh 100000h~10FFFFh 110000h~11FFFFh 120000h~12FFFFh 130000h~13FFFFh 140000h~14FFFFh 150000h~15FFFFh 160000h~16FFFFh 170000h~17FFFFh 180000h~18FFFFh 190000h~19FFFFh 1A0000h~1AFFFFh 1B0000h~1BFFFFh 1C0000h~1CFFFFh 1D0000h~1DFFFFh 1E0000h~1EFFFFh 1F0000h~1FFFFFh www..com BA5 BA6 BA7 BK0 BA8 BA9 BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 BA21 BA22 BA23 BK1 BA24 BA25 BA26 BA27 BA28 BA29 BA30 BA31 2008-07-24 F-37/47 TC58FVM7(T/B)DD 10.1. TC58FVM7TDD (Top Boot Block) 2/5 BLOCK ADDRESS BANK # BLOCK # BANK ADDRESS A22 BA32 BA33 BA34 BA35 BA36 BA37 BA38 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A21 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A20 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H A19 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H A18 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H A17 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H A16 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H A15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ADDRESS RANGE A14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 200000h~20FFFFh 210000h~21FFFFh 220000h~22FFFFh 230000h~23FFFFh 240000h~24FFFFh 250000h~25FFFFh 260000h~26FFFFh 270000h~27FFFFh 280000h~28FFFFh 290000h~29FFFFh 2A0000h~2AFFFFh 2B0000h~2BFFFFh 2C0000h~2CFFFFh 2D0000h~2DFFFFh 2E0000h~2EFFFFh 2F0000h~2FFFFFh 300000h~30FFFFh 310000h~31FFFFh 320000h~32FFFFh 330000h~33FFFFh 340000h~34FFFFh 350000h~35FFFFh 360000h~36FFFFh 370000h~37FFFFh 380000h~38FFFFh 390000h~39FFFFh 3A0000h~3AFFFFh 3B0000h~3BFFFFh 3C0000h~3CFFFFh 3D0000h~3DFFFFh 3E0000h~3EFFFFh 3F0000h~3FFFFFh www..com BA39 BK2 BA40 BA41 BA42 BA43 BA44 BA45 BA46 BA47 BA48 BA49 BA50 BA51 BA52 BA53 BA54 BA55 BK3 BA56 BA57 BA58 BA59 BA60 BA61 BA62 BA63 2008-07-24 F-38/47 TC58FVM7(T/B)DD 10.1. TC58FVM7TDD (Top Boot Block) 3/5 BLOCK ADDRESS BANK # BLOCK # BANK ADDRESS A22 BA64 BA65 BA66 BA67 BA68 BA69 BA70 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A21 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A20 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H A19 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H A18 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H A17 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H A16 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H A15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ADDRESS RANGE A14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 400000h~40FFFFh 410000h~41FFFFh 420000h~42FFFFh 430000h~43FFFFh 440000h~44FFFFh 450000h~45FFFFh 460000h~46FFFFh 470000h~47FFFFh 480000h~48FFFFh 490000h~49FFFFh 4A0000h~4AFFFFh 4B0000h~4BFFFFh 4C0000h~4CFFFFh 4D0000h~4DFFFFh 4E0000h~4EFFFFh 4F0000h~4FFFFFh 500000h~50FFFFh 510000h~51FFFFh 520000h~52FFFFh 530000h~53FFFFh 540000h~54FFFFh 550000h~55FFFFh 560000h~56FFFFh 570000h~57FFFFh 580000h~58FFFFh 590000h~59FFFFh 5A0000h~5AFFFFh 5B0000h~5BFFFFh 5C0000h~5CFFFFh 5D0000h~5DFFFFh 5E0000h~5EFFFFh 5F0000h~5FFFFFh www..com BA71 BK4 BA72 BA73 BA74 BA75 BA76 BA77 BA78 BA79 BA80 BA81 BA82 BA83 BA84 BA85 BA86 BA87 BK5 BA88 BA89 BA90 BA91 BA92 BA93 BA94 BA95 2008-07-24 F-39/47 TC58FVM7(T/B)DD 10.1. TC58FVM7TDD (Top Boot Block) 4/5 BLOCK ADDRESS BANK # BLOCK # BANK ADDRESS A22 BA96 BA97 BA98 BA99 BA100 BA101 BA102 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A21 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A20 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H A19 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H A18 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H A17 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H A16 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L A15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ADDRESS RANGE A14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 600000h~60FFFFh 610000h~61FFFFh 620000h~62FFFFh 630000h~63FFFFh 640000h~64FFFFh 650000h~65FFFFh 660000h~66FFFFh 670000h~67FFFFh 680000h~68FFFFh 690000h~69FFFFh 6A0000h~6AFFFFh 6B0000h~6BFFFFh 6C0000h~6CFFFFh 6D0000h~6DFFFFh 6E0000h~6EFFFFh 6F0000h~6FFFFFh 700000h~70FFFFh 710000h~71FFFFh 720000h~72FFFFh 730000h~73FFFFh 740000h~74FFFFh 750000h~75FFFFh 760000h~76FFFFh 770000h~77FFFFh 780000h~78FFFFh 790000h~79FFFFh 7A0000h~7AFFFFh 7B0000h~7BFFFFh 7C0000h~7CFFFFh 7D0000h~7DFFFFh 7E0000h~7EFFFFh www..com BA103 BK6 BA104 BA105 BA106 BA107 BA108 BA109 BA110 BA111 BA112 BA113 BA114 BA115 BA116 BA117 BA118 BK7 BA119 BA120 BA121 BA122 BA123 BA124 BA125 BA126 2008-07-24 F-40/47 TC58FVM7(T/B)DD 10.1. TC58FVM7TDD (Top Boot Block) 5/5 BLOCK ADDRESS BANK # BLOCK # BANK ADDRESS A22 BA127 BA128 BA129 BA130 BK7 BA131 BA132 BA133 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L H H L H L H 7F8000h~7F9FFFh 7FA000h~7FBFFFh 7FC000h~7FDFFFh 7FE000h~7FFFFFh H H H H A21 H H H H A20 H H H H A19 H H H H A18 H H H H A17 H H H H A16 H H H H A15 L L L L A14 L L H H A13 L H L H 7F0000h~7F1FFFh 7F2000h~7F3FFFh 7F4000h~7F5FFFh 7F6000h~7F7FFFh ADDRESS RANGE www..com BA134 2008-07-24 F-41/47 TC58FVM7(T/B)DD 10.2. TC58FVM7BDD (Bottom Boot Block) 1/5 BLOCK ADDRESS BANK # BLOCK # BANK ADDRESS A22 BA0 BA1 BA2 BA3 BK0 BA4 BA5 BA6 L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H H H L L H H L H L H 008000h~009FFFh 00A000h~00BFFFh 00C000h~00DFFFh 00E000h~00FFFFh L L L L A21 L L L L A20 L L L L A19 L L L L A18 L L L L A17 L L L L A16 L L L L A15 L L L L A14 L L H H A13 L H L H 000000h~001FFFh 002000h~003FFFh 004000h~005FFFh 006000h~007FFFh ADDRESS RANGE www..com BA7 2008-07-24 F-42/47 TC58FVM7(T/B)DD 10.2. TC58FVM7BDD (Bottom Boot Block) 2/5 BLOCK ADDRESS BANK # BLOCK # BANK ADDRESS A22 BA8 BA9 BA10 BA11 BA12 BA13 BA14 BK0 www..com BA15 BA16 BA17 BA18 BA19 BA20 BA21 BA22 BA23 BA24 BA25 BA26 BA27 BA28 BA29 BA30 BK1 BA31 BA32 BA33 BA34 BA35 BA36 BA37 BA38 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H L L L L H H H H L L H H L L H H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * ADDRESS RANGE A19 L L L L L L L H H H H H H H H L L L L L L L L A18 L L L H H H H L L L L H H H H L L L L H H H H A17 L H H L L H H L L H H L L H H L L H H L L H H A16 H L H L H L H L H L H L H L H L H L H L H L H A15 * * * * * * * * * * * * * * * * * * * * * * * A21 L L L L L L L L L L L L L L L L L L L L L L L A20 L L L L L L L L L L L L L L L H H H H H H H H A14 * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * L L L L L L L L L L L L L L L L L L L L L L L 010000h~01FFFFh 020000h~02FFFFh 030000h~03FFFFh 040000h~04FFFFh 050000h~05FFFFh 060000h~06FFFFh 070000h~07FFFFh 080000h~08FFFFh 090000h~09FFFFh 0A0000h~0AFFFFh 0B0000h~0BFFFFh 0C0000h~0CFFFFh 0D0000h~0DFFFFh 0E0000h~0EFFFFh 0F0000h~0FFFFFh 100000h~10FFFFh 110000h~11FFFFh 120000h~12FFFFh 130000h~13FFFFh 140000h~14FFFFh 150000h~15FFFFh 160000h~16FFFFh 170000h~17FFFFh 180000h~18FFFFh 190000h~19FFFFh 1A0000h~1AFFFFh 1B0000h~1BFFFFh 1C0000h~1CFFFFh 1D0000h~1DFFFFh 1E0000h~1EFFFFh 1F0000h~1FFFFFh 2008-07-24 F-43/47 TC58FVM7(T/B)DD 10.2. TC58FVM7BDD (Bottom Boot Block) 3/5 BLOCK ADDRESS BANK # BLOCK # BANK ADDRESS A22 BA39 BA40 BA41 BA42 BA43 BA44 BA45 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A21 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A20 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H A19 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H A18 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H A17 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H A16 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H A15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ADDRESS RANGE A14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 200000h~20FFFFh 210000h~21FFFFh 220000h~22FFFFh 230000h~23FFFFh 240000h~24FFFFh 250000h~25FFFFh 260000h~26FFFFh 270000h~27FFFFh 280000h~28FFFFh 290000h~29FFFFh 2A0000h~2AFFFFh 2B0000h~2BFFFFh 2C0000h~2CFFFFh 2D0000h~2DFFFFh 2E0000h~2EFFFFh 2F0000h~2FFFFFh 300000h~30FFFFh 310000h~31FFFFh 320000h~32FFFFh 330000h~33FFFFh 340000h~34FFFFh 350000h~35FFFFh 360000h~36FFFFh 370000h~37FFFFh 380000h~38FFFFh 390000h~39FFFFh 3A0000h~3AFFFFh 3B0000h~3BFFFFh 3C0000h~3CFFFFh 3D0000h~3DFFFFh 3E0000h~3EFFFFh 3F0000h~3FFFFFh www..com BA46 BK2 BA47 BA48 BA49 BA50 BA51 BA52 BA53 BA54 BA55 BA56 BA57 BA58 BA59 BA60 BA61 BA62 BK3 BA63 BA64 BA65 BA66 BA67 BA68 BA69 BA70 2008-07-24 F-44/47 TC58FVM7(T/B)DD 10.2. TC58FVM7BDD (Bottom Boot Block) 4/5 BLOCK ADDRESS BANK # BLOCK # BANK ADDRESS A22 BA71 BA72 BA73 BA74 BA75 BA76 BA77 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A21 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L A20 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H A19 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H A18 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H A17 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H A16 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H A15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ADDRESS RANGE A14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 400000h~40FFFFh 410000h~41FFFFh 420000h~42FFFFh 430000h~43FFFFh 440000h~44FFFFh 450000h~45FFFFh 460000h~46FFFFh 470000h~47FFFFh 480000h~48FFFFh 490000h~49FFFFh 4A0000h~4AFFFFh 4B0000h~4BFFFFh 4C0000h~4CFFFFh 4D0000h~4DFFFFh 4E0000h~4EFFFFh 4F0000h~4FFFFFh 500000h~50FFFFh 510000h~51FFFFh 520000h~52FFFFh 530000h~53FFFFh 540000h~54FFFFh 550000h~55FFFFh 560000h~56FFFFh 570000h~57FFFFh 580000h~58FFFFh 590000h~59FFFFh 5A0000h~5AFFFFh 5B0000h~5BFFFFh 5C0000h~5CFFFFh 5D0000h~5DFFFFh 5E0000h~5EFFFFh 5F0000h~5FFFFFh www..com BA78 BK4 BA79 BA80 BA81 BA82 BA83 BA84 BA85 BA86 BA87 BA88 BA89 BA90 BA91 BA92 BA93 BA94 BK5 BA95 BA96 BA97 BA98 BA99 BA100 BA101 BA102 2008-07-24 F-45/47 TC58FVM7(T/B)DD 10.2. TC58FVM7BDD (Bottom Boot Block) 5/5 BLOCK ADDRESS BANK # BLOCK # BANK ADDRESS A22 BA103 BA104 BA105 BA106 BA107 BA108 BA109 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A21 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H A20 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H A19 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H A18 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H A17 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H A16 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H A15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ADDRESS RANGE A14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * A13 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 600000h~60FFFFh 610000h~61FFFFh 620000h~62FFFFh 630000h~63FFFFh 640000h~64FFFFh 650000h~65FFFFh 660000h~66FFFFh 670000h~67FFFFh 680000h~68FFFFh 690000h~69FFFFh 6A0000h~6AFFFFh 6B0000h~6BFFFFh 6C0000h~6CFFFFh 6D0000h~6DFFFFh 6E0000h~6EFFFFh 6F0000h~6FFFFFh 700000h~70FFFFh 710000h~71FFFFh 720000h~72FFFFh 730000h~73FFFFh 740000h~74FFFFh 750000h~75FFFFh 760000h~76FFFFh 770000h~77FFFFh 780000h~78FFFFh 790000h~79FFFFh 7A0000h~7AFFFFh 7B0000h~7BFFFFh 7C0000h~7CFFFFh 7D0000h~7DFFFFh 7E0000h~7EFFFFh 7F0000h~7FFFFFh www..com BA110 BK6 BA111 BA112 BA113 BA114 BA115 BA116 BA117 BA118 BA119 BA120 BA121 BA122 BA123 BA124 BA125 BA126 BK7 BA127 BA128 BA129 BA130 BA131 BA132 BA133 BA134 2008-07-24 F-46/47 TC58FVM7(T/B)DD 11. BLOCK SIZE TABLE 11.1. TC58FVM7TDD (Top Boot Block) BLOCK # BA0~BA15 BA16~BA31 BA32~BA47 BA48~BA63 BA64~BA79 BA80~BA95 BA96~BA111 BLOCK SIZE 64 Kwords x 16 64 Kwords x 16 64 Kwords x 16 64 Kwords x 16 64 Kwords x 16 64 Kwords x 16 64 Kwords x 16 64 Kwords x 15 BK7 BA127~BA134 8 Kwords x 8 1024Kwords 23 BANK # BK0 BK1 BK2 BK3 BK4 BK5 BK6 BANK SIZE 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords BLOCK COUNT 16 16 16 16 16 16 16 www..com BA112~BA126 11.2. TC58FVM7BDD (Bottom Boot Block) BLOCK # BA0~BA7 BA8~BA38 BA39~BA70 BA71~BA102 BA103~BA134 BA135~BA166 BA167~BA198 BA199~BA230 BA231~BA262 BLOCK SIZE 8 Kwords x 8 BK0 64 Kwords x 15 64 Kwords x 16 64 Kwords x 16 64 Kwords x 16 64 Kwords x 16 64 Kwords x 16 64 Kwords x 16 64 Kwords x 16 BK1 BK2 BK3 BK4 BK5 BK6 BK7 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 1024Kwords 16 16 16 16 16 16 16 1024Kwords 23 BANK # BANK SIZE BLOCK COUNT 2008-07-24 F-47/47 |
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